1. Field of the Invention
The present invention relates generally to a switched-current resistor (SCR) programmable gain array (PGA) targeted for wireless local area network (WLAN) applications. More specifically, embodiments of the present invention relate to an SCR PGA, where an SCR array may be employed in parallel with a feedback resistor to achieve constant bandwidth transient-free gain control.
2. Background Art
The rapid evolution of CMOS technology has accelerated the integration of mixed-signal systems, such as the wireless transceiver on a single chip. In the case of a zero intermediate-frequency (IF) or low IF receiver architecture targeted toward IEEE 802.11 a/b/g WLAN applications, signal levels arriving at the baseband are scaled to around a 0 dBm range for analog-to-digital conversion. With technology scaling, capacitive coupling in a zero IF receiver would increase enough to contribute to the de-offset problem. The dc-offset problem may be mitigated through the employment of a low-IF receiver, which also allows for increased integration. However, appropriate design of constituent circuits is vital under low voltage (LV) constraints.
FIG. 1 shows the block diagram of a low-IF receiver 100 in a dual-receive conversion configuration. The receiver 100 may include a Radio Frequency (RF) input 105, a Low Noise Amplifier (LNA) 110 followed by a mixer 115 with a Local Oscillator Reference Frequency (LORF) in the RF range. Due to the difference in the “in-phase” I and the “quadrature” Q signal, mixers 120 and 125 may have different IF reference frequencies (LOIF (I) and LOIF (Q)). Baseband channel selection filters 130 and 135, and the PGAs 140 and 145, complete the typical low IF receiver block diagram. PGAs are usually standard inverting amplifiers employing a switched-resistor bank for gain control. Terminals 150 and 155 constitute the output. A single synthesizer may synthesize both the IF and RF Local Oscillator (LO) frequencies.
The dynamic-range requirement from the antenna (input terminal 105) to the baseband may approximately equal 0 to 80 dB, with the majority of the gain achieved in the baseband. If the radio front-end offers a 0 to 30 dB range, the baseband channel selection filters 130 and 135, along with the PGAs 140 and 145 have to offer another 0 to 50 dB of controllable gain. Although cascading multiple PGAs may lead to such high gain ranges, excess bandwidths are required of the PGAs, sometimes equal to ten times the bandwidth of the channel-selection filters, to ensure stable selectivity against gain.
Technology scaling within submicron scales, when accompanied with a standard power supply, may not necessitate a significant change in the design of analog blocks. FIG. 2(a) shows a standard inverting amplifier 250 employing a switched-resistor bank Rfb 220 for gain control, which serves as a PGA 200. However, in tune with the burgeoning sub-volt nanoscale processes, the classic switched-resistor PGA 200 shown in FIG. 2(a) may be rendered ineffectual because of insufficient LV headroom.
One way to render an inverting amplifier 250 suitable for a minimum drain supply voltage (VDD) is to use a level shifter. As shown in FIG. 2(a), an extra input common-mode feedback (I-CMFB) 270 may explicitly bias the virtual ground Vvg+ and Vvg− to a common-mode voltage Vcm,in, which is the minimum saturation voltage VDSsat (typically 0.1 V) necessary for the transistor to act as a current sink Ib 260. The lowest possible VDD may be estimated by taking into account the voltage requirement into the input stage 252 (see the p-MOS differential pair 252 in FIG. 2(b)), and may be expressed as:VDD>|VT,p+|2VSDsat+2VDSsat,  (1)where VT,p is the p-channel transistor threshold voltage, and VSDsat is the source-drain saturation voltage. FIG. 2(b) shows the input 252 and output 254 stages of the inverting amplifier 250 of the PGA 200.
For a VT,p of −0.65 V, the lowest possible VDD is approximately 1V. The output 254 stage of the inverting amplifier 250 may be a typical class-A amplifier 254 (see FIG. 2(b)), which delivers a high swing output by locking the output-common mode voltage (Vcm,out) to VDD/2. SS in FIG. 2(b) refers to signal swing. However, a large output swing may require an output common-mode feedback (O-CMFB) 290. For example, a resistive detector may be required to extract Vcm,out for conversion into a current signal for the back-end current amplifier. Gain tuning may be accomplished by varying either the feed-forward resistor Rff 215 or the feedback resistor Rfb 220 via a switched-resistor bank comprising n-MOS transistor switches and associated resistors. Resistor 215 may also be included in the non-inverting terminal and resistor 220 in the feedback loop thereof. Therefore, the resistors in the non-inverting terminal and the feedback loop thereof are intentionally left unlabeled. The switches may be placed at Vvg+ and Vvg− to gain enough overdrive voltage (VOD) of roughly 0.3V. VOD may be expressed as:VOD=VDD−VT,n−VDS,sat,  (2)where VT,n is the n-channel transistor threshold voltage.
Additionally, two distinct reference voltages, Vref,in 272 of 0.1 V and Vref,out 285 of 0.5 V may be required (see FIG. 2(a)). Resistors 255 and 275 refer to Rcm,in and Rcm,out respectively, and resistors 265 and 280 appropriately refer to Rcm,in/2 and Rcm,out/2 respectively. Terminals 205 and 210 constitute the input (Vin+ and Vin−) of the PGA 200, and terminals 292 and 294 constitute the output (Vout+ and Vout−). Amplifiers 267 and 268 are constituent elements of I-CMFB 270 and O-CMFB 290 respectively. Vref,out 285 should be buffered in order to be able to drive the O-CMFB 290 that drains static current.